1. Field of the Invention
The invention relates generally to semiconductor power devices. More particularly, this invention relates to configurations and methods to manufacture lateral power device including a super-junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance.
2. Description of the Prior Art
Conventional semiconductor power device such as the MOSFET power devices implemented with a super-junction structure can achieve performance improvements with significant reduction of the on-resistance while still maintaining a high breakdown voltage. However, the manufacturing technologies and device configuration for implementing the super-junction structures in the MOSFET devices are still confronted with manufacturability difficulties. The manufacturing ease and cost of the conventional vertical high voltage power devices implemented with super-junction structures are limited due to the structural features that require numerous time-consuming, complex, and expensive manufacturing processes. The current practice involves many sequential masking, implantation and epitaxial growth steps to build the vertical structure. Achieving a high density of alternately doped columns becomes prohibitive since it requires a direct increase in the number of these steps. Too many factors influence the accuracy of charge-balance between adjacent alternately doped columns, leading to narrow process margins as a high density of said columns is attempted. FIG. 1A shows a typical design for a MOSFET vertical super junction device, as disclosed by Tatsuhiko Fujihira in his paper “Theory of Semiconductor Superjunction Devices” published in Jpn. J. Appl. Phys. 36 (1997) pp. 6254-6262. It is difficult and costly to manufacture the vertical charge-balanced alternately doped columns of FIG. 1A, especially at high densities.
For these reasons, lateral JFET power devices with super junction structures formed with stacked horizontal layers of alternating dopant conductivity types overcome these difficulties. This device may be configured in cascade with a low voltage MOSFET to achieve the normally-off operation of a conventional device. Coe discloses a lateral power device in U.S. Pat. No. 4,754,310 with charge balanced super junction structure configured with stacked horizontal layers of alternating conductivity types extended between a source and drain column. Such structure of stacked horizontal layers can be efficiently manufactured without the use of masks. However, a typical device configuration as shown in FIG. 1B is limited by its drain-substrate breakdown voltage and is further restricted due to the difficulty in improving its unclamped inductive switching (UIS). FIG. 1C shows an example of another lateral super junction device as disclosed by Tatsuhiko Fujihira in the same paper as mentioned above, “Theory of Semiconductor Superjunction Devices”. This device suffers from excessive channel resistance in distributing the current into the stacked n-type conduction paths.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new device configurations and manufacturing methods for forming the lateral power device such that the above discussed problems and limitations can be resolved.